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| DRAM MODULE M374F320(8)0DJ1-C M374F320(8)0DJ1-C EDO Mode without buffer 32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V GENERAL DESCRIPTION The Samsung M374F320(8)0DJ1-C is a 32Mx72bits Dynamic RAM high density memory module. The Samsung M374F320(8)0DJ1-C consists of thirty-six CMOS 16Mx4bits DRAMs in SOJ 400mil packages and one 1K/2K EEPROM for SPD in 8-pin SOP package mounted on a 168-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M374F320(8)0DJ1-C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. FEATURES * Part Identification Part number M374F3200DJ1-C M374F3280DJ1-C * * * * * * * * PK SOJ SOJ Re 4K 8K CBR ref. ROR ref. 4K/64ms 4K/64ms 8K/64ms PERFORMANCE RANGE Speed -C50 -C60 tRAC 50ns 60ns tCAC 13ns 15ns tRC 84ns 104ns tHPC 20ns 25ns New JEDEC standard proposal without buffer Serial Presence Detect with EEPROM Extended Data Out Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability LVTTL compatible inputs and outputs Single +3.3V0.3V power supply PCB : Height(1625mil), double sided component PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front Pin VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC W0 CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU VSS OE2 RAS2 CAS2 CAS3 W2 VCC NC NC CB2 CB3 VSS DQ16 DQ17 Pin Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC DU CAS4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back CAS5 RAS1 DU VSS A1 A3 A5 A7 A9 A11 *A13 VCC DU DU VSS DU RAS3 CAS6 CAS7 DU VCC NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC PIN NAMES Pin Name A0 - A11 A0 - A12 DQ0 - DQ63 W0, W2 OE0, OE2 RAS0 - RAS3 CAS0 - CAS7 VCC VSS NC DU SDA SCL SA0 -SA2 CB0 - CB7 Function Address Input(4K ref.) Address Input(8K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+3.3V) Ground No Connection Dont use Serial Address /Data I/O Serial Clock Address in EEPROM Check Bit * These pins are not used in this module. NOTE : A12 is used for only M374F3280DJ1-C (8K ref.) REV. 0.1 Oct. 2000 DRAM MODULE FUNCTIONAL BLOCK DIAGRAM RAS0 W0 OE0 A0-A11(A12) CAS0 U0 M374F320(8)0DJ1-C RAS3 W2 OE2 CAS4 DQ0 DQ1 DQ2 DQ3 DQ36~39 DQ0 DQ1 DQ2 DQ3 DQ8~11 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ16~19 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U19 U10 U27 RAS1 RAS2 DQ0~3 DQ0 DQ1 DQ2 DQ3 DQ4~7 U1 DQ32~35 DQ0 DQ1 DQ2 DQ3 U18 U9 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ46~51 DQ40~43 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U28 CAS1 CAS5 U2 U20 U11 U29 DQ12~15 DQ44~45 U3 U21 U12 U30 CB0~3 U4 U22 U13 CB4~7 U31 CAS2 U5 CAS6 U32 U23 U14 DQ20~23 DQ52~55 U6 U24 U15 U33 CAS3 U7 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ24~27 DQ0 DQ1 DQ2 DQ3 DQ28~31 DQ0 DQ1 DQ2 DQ3 U25 U16 DQ56~59 CAS7 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 U34 DQ60~63 U8 U26 U17 U35 NOTE : A12 is used for only M374F3280DJ1 (8K ref.) VCC 0.1 or 0.22uF Capacitor under each DRAM Vss To all DRAMs SCL Serial PD A0 A1 A2 SDA SA0 SA1 SA2 REV. 0.1 Oct. 2000 DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS M374F320(8)0DJ1-C Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 36 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width15ns which is measured at VCC. *2 : -1.3V at pulse width15ns which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care M374F3280DJ1 Min - M374F3200DJ1 Max Min -10 -10 2.4 Max 1998 1818 36 1998 1818 1638 1458 18 1998 1818 10 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V 1458 1278 36 1458 1278 1638 1458 18 1998 1818 10 10 0.4 -10 -10 2.4 - ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVCC) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. REV. 0.1 Oct. 2000 DRAM MODULE CAPACITANCE (TA = 25C, VCC=3.3V, f = 1MHz) Item Input capacitance[A0-A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0-DQ63, CB0-CB7] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - M374F320(8)0DJ1-C Max 190 136 73 52 27 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period (4K & 8K Ref.) Write command set-up time CAS to W delay time RAS to W delay time Symbol -50 Min 84 128 50 13 25 3 3 3 1 30 50 8 38 8 17 12 5 0 7 0 7 25 0 0 0 7 7 8 7 0 7 64 0 33 70 0 38 84 10K 37 25 10K 13 50 3 3 3 1 40 60 10 40 10 20 15 5 0 10 0 10 30 0 0 0 10 10 10 10 0 10 64 10K 45 30 10K 13 50 Max Min 104 153 60 15 30 -60 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 7 7 7 8 8 4 9 3,4,9 3,4,5 3,9 3 3 6,10 2 Note tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD REV. 0.1 Oct. 2000 DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Column address to W delay time CAS precharge to W delay time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper page cycle) Symbol -50 Min 45 47 5 10 5 28 20 67 7 50 30 13 10 3 5 5 3 3 15 5 5 5 5 13 13 13 13 3 5 5 3 3 15 5 5 5 5 200K 25 73 10 60 35 Max Min 53 58 5 10 5 M374F320(8)0DJ1-C -60 Max Unit ns ns ns ns ns Note 7 tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 35 ns ns ns ns 3 11 11 200K 15 13 ns ns ns ns ns ns ns 6 13 13 ns ns ns ns ns ns ns 6,10 6 REV. 0.1 Oct. 2000 DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non-restrictive operating parameter. They are inclueded in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. If neither of the above contitions are satisfied, The condition of the data out is indeternimated. M374F320(8)0DJ1-C 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 10. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condtion of the output is achieved by RAS high going. 11. tASC6ns. REV. 0.1 Oct. 2000 DRAM MODULE READ CYCLE M374F320(8)0DJ1-C tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA DQ VOH VOL - tRAC OPEN tOLZ tCAC tCLZ tREZ DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M374F320(8)0DJ1-C tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN M374F320(8)0DJ1-C tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE READ - MODIFY - WRITE CYCLE M374F320(8)0DJ1-C tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tASR VIH VIL - tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ VI/OH VI/OL - Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ CYCLE M374F320(8)0DJ1-C tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC ROW ADDR tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCPA tCAC tOEA tCAC tAA tCPA tOCH tOEA tOEP tDOH VALID DATA-OUT tCAC tAA tCHO tOEP tAA OE VIH VIL - tCAC tRAC DQ VOH VOL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M374F320(8)0DJ1-C tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o o o tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE M374F320(8)0DJ1-C RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tCRP CAS VIH VIL - tCAH tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tCWD tAWD tRWD tOEA tCAC tAA tRAC tCAC OE VIH VIL - tOED tDH tDS tAA tDH tOEZ tDS tOEZ DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE M374F320(8)0DJ1-C tRASP RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS COL. ADDR tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH VIL - M374F320(8)0DJ1-C tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) M374F320(8)0DJ1-C tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN M374F320(8)0DJ1-C tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE M374F320(8)0DJ1-C tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. REV. 0.1 Oct. 2000 DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care M374F320(8)0DJ1-C tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCSR tCHS tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE PACKAGE DIMENSIONS M374F320(8)0DJ1-C Units : Inches (millimeters) 6.000 (152.400) 5.250 (133.350) 5.014 (127.350) 0.95 (24.13) 0.118 (3.000) 0.054 (1.372) R 0.079 (R 2.000) 1.625 (41.28) 0.95 (24.13) R 0.055(1.40) 0.118 0.118 (3.000) (3.000) 0.1570.004 (4.0000.100) (17.780) 0.350Max (8.89Max) 0.0500.0039 (1.2700.10) (2.540 Min) 0.700 0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) .118DIA.004 (3.000DIA.100) 0.350 (8.890) ( Front view ) ( Back view ) 0.250 (6.350) 0.100 Min 0.250 (6.350) 0.100Min (2.540Min) 0.039.002 (1.000.050) 0.008.0.006 (0.200.0.150) 0.050 (1.270) A B C 0.1230.0050 (3.125.125) 0.1230.0050 (3.125.125) 0.079.0040 (2.000.100) 0.079.0040 (2.000.100) Detail A Tolerances : .005(.13) unless otherwise specified The used device is 16Mx4 DRAM with EDO mode, SOJ DRAM Part No. : M374F3280DJ1-K4E660412D-J M374F3200DJ1-K4E640412D-J Detail B Detail C REV. 0.1 Oct. 2000 |
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